1. Field of the Invention
The present invention is related to a semiconductor memory device such as a dynamic random access memory (DRAM). Especially, the present invention is related to a structure of the semiconductor memory device and a method of fabricating the same.
2. Description of the Related Art
A memory cell of a semiconductor memory device is often constituted by a capacitor and a MOS (Metal Oxide Semiconductor) transistor. Such a memory cell is called 1T-1C cell. A dynamic random access memory (DRAM) includes a memory cell array in which 1T-1C cells are arranged in rows and columns.
FIG. 1 shows 1T-1C memory cells included in a conventional semiconductor memory device. The conventional semiconductor memory device is provided with MOS transistors formed in a surface portion of a P-type silicon substrate 100. The MOS transistors include gate oxide films 110, gate electrodes 103, N-type source regions 113, N-type drain region 114, LDD (lightly doped drain) regions 111, and sidewalls 112. The gate electrodes 103 function as word lines of the memory device. To reduce the contact resistance, a cobalt silicide technique is adapted to the memory device. Cobalt silicide layers 132 are formed in the surface portion of the source regions 113, and another cobalt silicide layers 132xe2x80x2 is formed in the surface portion of the drain region 114. In addition, still another cobalt silicide layer 133 is formed in the surface portion of the gate electrodes 103. MOS transistors are electrically isolated from other elements (not shown) by STI (shallow trench isolation) dielectrics 101.
The MOS transistors and the STI dielectrics 101 are covered with a silicon nitride film 115 and an inter-level dielectric 116. The silicon nitride film 115 and the inter-level dielectric 116 are penetrated by capacitor plugs 104 formed of heavily doped polysilicon.
The inter-level dielectric 116 is covered with an inter-level dielectric 122. The inter-level dielectric 122 are provided with holes to accommodate the memory cell capacitors.
Each of the memory cell capacitors includes a bottom electrode 106, a dielectric layer 107, a titanium nitride layer 108, and a polysilicon layer 109. The bottom electrode 106 is formed of heavily doped polysilicon. The bottom electrode 106 is electrically connected to the source region 113 through the capacitor plug 104. The dielectric layer 107 is formed of tantalum oxide on the bottom electrode 106. The titanium nitride layer 108 and the polysilicon layer 109 functions as an upper electrode of the memory cell capacitor.
The inter-level dielectric 122 and the memory cell capacitors are covered with an inter-level dielectric 135. A bit line 131 formed of titanium nitride is formed on the inter-level dielectric 135.
A bit line contact plug 102 is formed through the inter-level dielectric 116, 122, and 135 to electrically connect the bit line 131 to the drain region 114 of the MOS transistors.
To access the memory cell, the bit line 131 is firstly set at a predetermined potential. Then, the gate electrode 103 is pulled up to activate the MOS transistor. The activation of the MOS transistor allows an exchange of charges between the bit line 131 and the memory cell capacitors through the bit line contact plugs 102, the MOS transistors and the capacitor plug 104, The exchange of the charges causes a change in the potential of the bit line 131. The potential of the bit line 131 is detected to define the data stored in the memory cell.
In the conventional memory device, the capacitor plugs 104, formed of doped polysilicon, increases the resistance between the bit line 131 and the bottom electrodes 106 of the memory cell capacitors. This decreases the access speed of the memory device. The resistance between the bit line 102 and the memory cell capacitors is desirably decreased.
In addition, the conventional memory device requires an etching technique to form a contact hole having a high aspect ratio. Before forming the bit line contact plug 102, a contact hole having a high aspect ration is necessary to be formed from the surface of the inter-level dielectric 135 to the drain region 114 of the MOS transistors. The necessity of forming a high-aspect-ratio contact hole makes the fabricating process difficult.
Yamanaka et al. disclose another semiconductor memory device for improving reliability and reducing a size of memory cells thereof in PCT Gazette (WO 09/28795). The semiconductor memory includes a memory cell region and a logical circuit region. The memory cell region includes a first transistor, and the logical circuit region includes second and third transistors that operate complementarily. The first, second and third transistors are covered with a dielectric. An interconnection of metal is formed on the dielectric over the memory cell region and the logical circuit region. Electrical connection between the interconnection and the first, second, and third transistor is achieved by a contact including a conductor formed in a hole fabricated through the dielectric. Yamanaka et al. discloses that the conductor included in the contact is formed of titanium nitride or titanium tungsten.
Shen et al. disclose still another semiconductor memory device for facilitating the fabrication process of a memory cell in U.S. Pat. No. 6,136,660 and Japanese Laid Open Patent Application (JP-A 2000-114475) corresponding thereto. The memory cell includes a field effect transistor and a stacked capacitor. The stacked capacitor has one plate formed by a platinum layer over the side walls of a portion of a dielectric layer that overlies a conductive layer that makes contact to a conductive plug connected to the storage node of the cell. The capacitor dielectric overlies the sidewalls and top of the dielectric layer portion and the other plate of the capacitor is formed by a platinum layer over the capacitor dielectric.
Ohno discloses still another semiconductor memory device having a cylindrical MIM (Metal Insulator Metal) structured capacitor for reducing junction leak, capacitance loss and reaction between silicon and electrode material in Japanese Laid Open Patent Application (JP-A 2000-156479). The memory device is provided with a semiconductor substrate on which an active element is formed. The semiconductor substrate is covered with an interlayer insulation film. A contact hole is formed through the interlayer insulation film to reach the active element. A plug made of conductive material is formed in the contact hole. A barrier layer is formed on the interlayer insulation film for covering at least an upper portion of the plug. A cylindrical bottom electrode is formed on the plug. A dielectric is formed on the bottom electrode, and an upper electrode is formed on the dielectric.
Saitoh et al. disclose still another semiconductor memory device having a COB (capacitor over bit line) structure for preventing defects in the fabrication process in Japanese Laid Open Patent Application (JP-A-Heisei 11-214644). The semiconductor memory device is provided with a first insulating film formed of silicon oxide on a semiconductor substrate. An interconnection is formed on the first insulating film. The interconnection is covered with a second insulating film. A memory cell capacitor including a high-∈ dielectric is formed on the second insulating film. The interconnection includes a conductive layer in contact with the first insulating film, the conductive layer being formed of refractory metal other than titanium, or refractory metal nitride.
An object of the present invention is to increase an access speed of a semiconductor memory by reducing a resistance between a bit line and memory cell capacitors.
Another object of the present invention is to facilitate the fabrication process of a semiconductor memory by avoid forming a contact hole having a high aspect ratio.
Still another object of the present invention is to improve reliability of a semiconductor device by preventing a short circuit between capacitor electrodes of memory cell capacitors.
In accordance with an aspect of the present invention, a semiconductor memory device is composed of a substrate, a MOS (metal oxide semiconductor) transistor formed in a surface portion of the substrate, a first inter-level dielectric covering the MOS transistor, a capacitor element, and a first contact formed through the first inter-level dielectric. The capacitor element includes a bottom electrode, a dielectric layer formed on the bottom electrode, and an upper electrode formed on the dielectric layer. The first contact electrically connects the bottom electrode to the source of the MOS transistor. The first contact includes a first metal portion formed of metal.
When the metal is refractory metal, the first contact preferably further includes a barrier layer formed between the source the MOS transistor and the first metal portion.
The refractory metal is preferably tungsten, and the contact barrier layer is preferably formed of titanium nitride.
The bottom electrode preferably includes a polysilicon layer connected to the dielectric layer, and an electrode barrier layer formed between the first metal portion and the polysilicon layer. In this case, the electrode barrier layer is preferably formed of titanium nitride.
The semiconductor memory device is preferably further composed of a second contact formed through the first inter-level dielectric to be connected to the drain of the MOS transistor, the second contact including a second metal portion formed of the same metal as the first metal portion.
When the metal used for the first and second metal portions is tungsten, the second contact preferably further includes a second barrier layer formed of titanium nitride between the drain of the MOS transistor and the second metal portion.
In this case, the semiconductor memory device is preferably further composed of a second inter-level dielectric covering the capacitor element and the first inter-level dielectric, a third contact formed through the second inter-level dielectric, and a bit line formed on the second inter-level dielectric, the second and third contact electrically connecting the drain of the MOS transistor to the bit line.
When the semiconductor memory device is further composed of another MOS transistor provided in a surface portion of the substrate for a peripheral circuit, the semiconductor memory device preferably composed o a fourth contact formed through the first inter-level dielectric to be connected to the other MOS transistor on a source/drain thereof, a fifth contact formed through the second inter-level dielectric to be connected to the fourth contact, the fourth contact including a third metal portion formed of the metal.
The bottom electrode is preferably composed of a polysilicon layer connected to the dielectric layer, and an electrode barrier layer formed between the first metal portion and the polysilicon layer.
In this case, the electrode barrier layer is preferably formed of titanium nitride.
When the semiconductor memory device is further composed of a second inter-level dielectric covering the first inter-level dielectric and a hole is formed through the second inter-level dielectric, it is preferable that the electrode barrier layer preferably includes a bottom barrier portion formed on the metal portion of the first contact, and a side barrier portion connected to the bottom barrier portion, the side barrier portion being formed on a side surface of the hole to extend towards an upper surface of the second inter-level dielectric, and that the polysilicon layer includes a bottom electrode portion formed on the bottom barrier portion, and a side electrode portion connected to the bottom electrode portion, the side electrode portion being formed on the side barrier portion, and that an end of the side electrode portion is substantially in alignment with the upper surface of the second inter-level dielectric, while an end of the side barrier portion is out of alignment with the upper surface of the second inter-level dielectric, the side barrier portion not reaching the upper surface of the second inter-level dielectric.
In accordance with another aspect of the present invention, a method of fabricating a semiconductor memory device is composed of:
providing a substrate;
forming a MOS transistor in a surface portion of the substrate, wherein the MOS transistor includes a gate, a source, and a drain;
forming a first inter-level dielectric to cover the MOS transistor;
forming a first contact through the first inter-level dielectric such that the first contact is connected to the source of the MOS transistor, wherein the first contact includes a first metal portion formed of metal;
forming a bottom electrode connected to the first contact;
forming a dielectric layer formed on the bottom electrode;
forming an upper electrode formed on the dielectric layer.
The method is preferably further composed of:
forming a second inter-level dielectric to cover the first inter-level dielectric and the first contact;
forming a hole through the second inter-level dielectric to expose the first contact, the forming the bottom electrode including:
depositing a conductive barrier material film on a side surface and bottom surface of the hole,
depositing a polysilicon film on the conductive barrier material film,
concurrently removing outside portions of the conductive barrier material film and the polysilicon film outside the hole to form the electrode barrier layer and the polysilicon layer, and
selectively etching an end portion of the electrode barrier layer in the vicinity of an upper surface of the second inter-level dielectric such that an end of the conductive barrier material film does not reach the upper surface of the second inter-level dielectric, while the polysilicon layer is not etched.
In this case, the method is preferably further composed of:
forming a resist layer on the polysilicon film to plug the hole after the depositing the polysilicon film, wherein the layer is used as a mask for the concurrently etching; and
removing the resist layer by a plasma process in an atmosphere including fluorocarbon, wherein the selectively etching is concurrently achieved during the removing the resist layer.
Also, the method is preferably further composed of:
forming an etching stopper layer to cover the first contact and the first inter-level dielectric;
forming a second inter-level dielectric on the etching stopper layer;
etching the second inter-level dielectric to expose a portion of the etching stopper layer, wherein the etching the second inter-level dielectric is stopped by the etching stopper layer;
etching the etching stopper layer to the first contact to form a hole penetrating the second inter-level dielectric and the etching stopper layer, wherein the bottom electrode, the dielectric layer, and the upper electrode are disposed inside the hole.
Moreover, the method is preferably further composed of:
forming a second contact formed through the first inter-level dielectric to be connected to the drain, the second contact including a second metal portion formed of the metal, wherein the first and second contacts are concurrently formed; and
forming a bit line, wherein the bit line is electrically connected to the drain through the second contact.
In this case, the method is preferably further composed of:
forming another MOS transistor in a surface portion of the substrate for a peripheral circuit;
forming a third contact formed through the first inter-level dielectric to be connected to a source/drain region of the another MOS transistor, the third contact including a third metal portion formed of the metal, wherein the first, second and third contacts are concurrently formed; and
forming an interconnection, wherein the interconnection is electrically connected to the source/drain region through the third contact.